1. Field of the Invention
The present invention relates to a fabricating method of semiconductor devices such as LSIs, and in particular, to semiconductor wafers before being diced, and a dicing method.
2. Related Art
When a semiconductor device is fabricated, a photoresist film is patterned by using a stepping projection aligner (a stepper). When the patterning is performed, it is required that an alignment mark formed in advance on the semiconductor substrate in the previous step is detected by using a laser, and the gap between the original coordinate and the actual coordinate (due to the accuracy of the stepper in the previous step, stretch distortion of the wafer, and the like) is corrected on the basis of a diffraction ray generated from the alignment mark, to thereby perform an alignment. Thus, an accessory pattern including the alignment mark or TEG (test element group) for characteristic evaluations is provided. The accessory pattern is formed (in a scribe line region) independent from a region on which elements such as transistors are formed (an element forming region), without increasing the chip area. The TEG consists of a number of elements for evaluating device characteristics, for example, evaluating characteristics of MOS transistors and measuring contact resistance.
In the final stage, the scribe line region is diced so as to divide the element forming regions into pieces.
Methods for dividing respective element forming regions are described in Japanese Patent Application Laid-open No. 6-45437 (JP6-45437A) and Japanese Patent Application Laid-open No. 2001-210609 (JP2001-210609A). In the method disclosed in JP 6-45437A, an A1 film is remained in between the semiconductor chip and an alignment mark in the scribe line, and the remained A1 film is covered with an overcoat film. Then, the overcoat film and the A1 film are diced with a dicing blade. In this method, there remains a problem that the overcoat film is adhered to the dicing blade so that the service life of the dicing blade becomes shortened.
In order to solve the aforementioned problem in the dicing method, a typical semiconductor wafer before being diced will be considered.
As shown in FIG. 1A, a semiconductor wafer 40 is provided with two divided regions on a substrate 41, that is, an element forming region 42 and a scribe line region 43 formed around the element forming region 42. In the scribe line region 43, an accessory pattern forming region 44 is provided, in which an accessory pattern consisting of a wiring layer is formed. Further, the element forming region 42 is covered with a protective film not shown.
On the element forming region 42, a semiconductor device such as an LSI is formed. The most part of the scribe line region 43 is chipped off when dicing. The accessory pattern may be an alignment mark for only being utilized during fabricating process, a TEG pad, or the like. By providing the accessory pattern forming region 44 not in the element forming region 42 but in the scribe line region 43, the area of the semiconductor chip can be reduced.
After the element forming region 42 is covered with the protective film, the scribe line region 43 is diced using a disk-shaped dicing blade. Thereby, the element forming regions 42 are divided into separate pieces of a semiconductor chip.
Next, the laminated structure of a DRAM and the specific configuration of the scribe line region 43 thereof will be explained. As shown in FIG. 1B, a DRAM is so formed that on a silicon substrate 50, an interlayer insulating layer 51, a top-layer wiring layer 52, and a photoresist layer 53a are laminated in sequence. Although FIG. 1B shows the scribe line region 43, this laminated structure is formed in the element forming region 42 as well.
The silicon substrate 50 is P-type. In the Figure, the thickness of the silicon substrate 50 is illustrated to be thinned comparing with the other parts, and only the scribe line region 43 is illustrated.
The interlayer insulating layer 51 consists of an SiO2 film, a TEOS(Tetra Ethyl Ortho Silicate)BPSG(Borophospho Silicate Glass) film, or the like, and has a thickness of about 4300 to 4800 nm, for example. Further, in the element forming region 42, the interlayer insulating layer 51 consists of an interlayer insulating film with at least three layers, such as an interlayer insulating film for insulating the element, the word line and the bit line from each other.
The top-layer wiring layer 52 is formed of a barrier metal layer 521 consisting of a Ti/TiN wiring layer with each thickness of about 30/100 nm, an A1 wiring layer 522 with a thickness of about 800 nm, and a reflection protective film 523 consisting of a TiN wiring layer with a thickness of about 25 nm.
As shown in FIGS. 2A and 2B, the top-layer wiring layer 52 is patterned by using the photo-lithography technique and the etching technique to thereby form a wiring (not shown) in the element forming region 42, and at the same time, to form an accessory pattern 53 at a desired position in the scribe line region 43.
The accessory pattern 53 includes an alignment mark or a TEG pad. The accessory pattern 53 shown is a TEG pad conducting to the TEG 54 for evaluating characteristics of MOS transistor, measuring contact resistance and the like.
Next, in order to reduce the trap level generated in the fabricating process, hydrogen alloy processing for annealing at 400 to 450° C. in H2 atmosphere is performed. Then, as shown in FIG. 2A, a passivation film 55 with a thickness of about 600 nm consisting of an SiON film or the like is formed over the whole surface. Finally, as shown in FIG. 3A, a polyimide film 56 is deposited across the element forming region 42 and the scribe line region 43. Therefore, the accessory pattern 53 formed in the scribe line region 43 is covered with the passivation film 55 and the polyimide film 56 in two layers laminated above and below.
In order to divide the element forming regions into pieces, the scribe line region 43 is diced with a dicing blade. It is required to prevent the dicing blade from being adhered with the polyimide film 56 to prolong the service life of the dicing blade.
In view of the above, as shown in FIGS. 3A and 3B, it may be possible to remove the passivation film 55 and the reflection preventive film 523 deposited on the bonding pad (not shown) formed on the top-layer wiring layer 52 in the element forming region 42, and to partially remove the reflection preventive film 523, the passivation film 55 and the polyimide film 56 in the scribe line region 43, by using the photolithography technique and the etching technique. This is a method to completely prevent the contact between a dicing blade and the polyimide film 56, and to remain the passivation film 55 and the polyimide film 56, continuing to the passivation film 55 and the polyimide film 56 formed in the element forming region 42, in the scribe line region 43 in the dimension of a width W11, and to completely expose the accessory pattern 53 in the scribe line region 43.
For example, the width W10 of an opening 57 is 90 μm, the width W11 of the polyimide film 56 in the scribe line region 43 has a width W11 of 5 μm, and the width 12 from the boundary between the scribe line region 43 and the element forming region 42 to the accessory pattern 53 is 10 μm. In the Figure, each dimension is symmetrical with reference to the center of the scribe line region 43.
However, as a result of dicing performed using the structure shown in FIGS. 3A and 3B, the accessory pattern 53 was subject to peeling or curling up (hereinafter referred to as “peeling or the like”) when being diced. This caused defects and a short of bonding wiring, whereby the yield dropped. With an identification of the cause, it was found that the accessory pattern 53 was formed on the interlayer insulating film 51, and when being diced with a dicing blade, the pattern was not supported in a fixed manner so it was in the free state.